Performance Analysis of Gated Ring Oscillator Designed for Audio Frequency Range Asynchronous Adc

This paper presents performance analysis of Gated Ring Oscillator (GRO). Proposed GRO is designed to employ in implementation of Time to Digital Converter (TDC) block of Asynchronous ADC. For an audio frequency range ADC, minimum GRO stages are designed using asynchronous technique. So leads to reduced area and power. Compared to conventional Ring Oscillator (RO), we avoided to employ the gated clock; to evade clock design related problems like jitter, additional area and power. Instead we preferred gating of ring oscillator itself. Consequently during sleep mode, GRO disables automatically which saves the dynamic power. Furthermore it also provides first order noise shaping of the quantization and mismatch noise. Proposed GRO is implemented with 0.18μm CMOS Digital Technology in Cadence Virtuso environment. GRO performance analysis shows oscillation frequency as 286 KHz with 327ps jitter and average power consumption of 1.08μW.